The present invention generally relates to semiconductor integrated circuit technology. More particularly, the present invention relates to an integrated circuit for reducing crosstalk and latch-up susceptibility.
In an integrated circuit (IC) having multiple devices monolithically built on the same substrate, unintended parasitic devices such as transistors, diodes or resistors are difficult to avoid and these parasitic devices cause undesirable crosstalk between devices. In a CMOS based integrated circuit using a p-substrate, for example, an n-well, the p-substrate, and another n region form a parasitic NPN transistor that could be turned on when one of the PN junctions in the transistor is forward-biased, thus causing latch-up of a device on the integrated circuit or even permanently damaging the integrated circuit. Latch-up is a condition in which a circuit draws uncontrolled amounts of current, and certain voltages are forced, or xe2x80x9clatched-up,xe2x80x9d to some undesirable and uncontrollable level that violates the operating conditions of the circuit. Latch-up conditions are most often caused by crosstalk between devices in an integrated circuit. Undesirable crosstalk between devices exists in bipolar integrated circuits, as well as field effect transistors such as a MOSFET.
The crosstalk and the related latch-up problem is particularly serious in smart power ICs. A smart power IC, or integrated power circuit, combines one or more power devices (such as high-voltage, high-powered transistors) with control circuits (such as low-voltage, low-power transistors) on the same chip. The smart power IC is fabricated monolithically, thus offering better performance, reduced cost, and increased reliability. Unfortunately, the above integration poses a threat of latch-up due to, for example, injection of minority carriers into the substrate caused by a forward-biased junction between a n-tub of a high-power device and the substrate. Such forward biasing conditions are often created by transient voltages induced during switching of the power device. One of the most important issues in smart power ICs is device interaction between devices. Such device interaction may occur between power devices, as well as between power devices and low voltage devices such as control devices. Wider and more efficient utilization of smart power IC technology will require a satisfactory technique to prevent such crosstalk that causes latch-up.
Various techniques exist in the art to reduce inter-device crosstalk. U.S. Pat. No. 4,466,011 to Zanten, for example, discloses an isolation structure in a bipolar integrated circuit to prevent leakage current from one component to another. In the bipolar integrated circuit of the above patent, elementary components are formed in islands of an N-type epitaxial layer surrounded by P-type isolation walls. The protection against leakage current is obtained by surrounding an island susceptible to receive negative voltage surges with an annular island of the same N-type epitaxial layer.
In smart power IC designs, attempts have also been made to improve isolation between devices. The proposed solutions include using a high resistivity substrate, or adding a series gate resistance to the gate driver circuitry (T. P. Chow, et al., xe2x80x9cInteraction between monolithic, junction isolated G lateral insulated-gate bipolar transistors,xe2x80x9d IEEE Trans. Electron Devices, Vol. 38, No. 2, pp. 310-315, 1991); using a floating well design (M. Bafleur, et al., xe2x80x9cApplication of a floating well concept to a latch-up free, low-cost, smart power high-side switch technology,xe2x80x9d IEEE Trans Electron Devices, Vol. 40, No. 7, pp. 1340-1342, 1993); introducing a high resistance layer on a portion of the upper surface of the substrate, either directly overlaying or adjacent to the power device (U.S. Pat. No. 6,255,710 to Weitzel et al.); and isolating the power device that induces latch-up with guard rings (W. Chan, et al., xe2x80x9cAn effective crosstalk isolation structure for power IC applications,xe2x80x9d IEDM Tech. Dig. 1995, pp. 971-974, and D. Rossi, xe2x80x9cPower MOSFETs driving circuits and protection techniques,xe2x80x9d in Smart Power ICs: Technologies and Applications, B. Murari et al., Eds, New York: Springer-Verlag, 1996, pp. 173-223).
Although the above attempts help alleviate the latch-up problem in smart power ICs, alternative methods and improvements are still necessary in smart power ICs particularly, chip designs and fabrication methods preferred or mandated by certain considerations such as performance and costs may be subject to induced minority carrier injections at much higher levels than those found in the CMOS structures shown in references such as the aforementioned article by W. Chan, et al. In addition, both biased and unbiased guard rings which surround the high-voltage device should be explored for better prevention of latch-up by reducing the gain of the parasitic substrate NPN that injects minority carriers into the substrate. References such as W. Chan, et al. indicated that biased rings in structures therein significantly outperform unbiased rings in terms of the effectiveness of the isolation. However, unbiased rings may be preferable because they avoid power consumption and interconnect requirements of biased guard rings. It is therefore particularly necessary to design an improved unbiased guard ring structure to prevent latch-up in smart power ICs.
The present invention is an integrated circuit having very low parasitic current gain. The integrated circuit is built on a monolithic semiconductor body material, and comprises a semiconductor epitaxial layer of a first type conductivity grown on a semiconductor substrate, a semiconductor device formed in the epitaxial layer, and a semiconductor central guard ring formed in the epitaxial layer. The central guard ring has a second type conductivity opposite to the first type conductivity and surrounds the semiconductor device. The integrated circuit further includes two flanking rings formed in the epitaxial layer. The two flanking rings have a lower resistivity than the epitaxial layer. The first flanking ring is disposed between the semiconductor device and the central guard ring, while the second flanking ring is disposed outside of the central guard ring. The two flanking rings thus xe2x80x9csandwichxe2x80x9d the central guard ring.
In one embodiment, the epitaxial layer and the substrate have the same type conductivity. The central guard ring, which has the opposite type conductivity, acts as a collector of minority carriers in the substrate, while the two flanking rings act as an isolator and a supplier for majority carriers, respectively. In another embodiment, the central guard ring is unbiased, the first flanking ring is grounded, and the central guard ring and the second flanking ring are shorted together. In one particular embodiment, the central guard ring is wider than any of the first and second flanking rings. These embodiments maximize the effectiveness of the guard ring structure in accordance with the present invention from different aspects.
In a further embodiment of the invention, the integrated circuit comprises a semiconductor body layer having a first type conductivity, a semiconductor device formed in the body layer, a semiconductor central guard ring formed in the body layer, and two flanking rings that are formed in the body layer but have a lower resistivity than the body layer. The central guard ring and two flanking rings surround the device. The first flanking ring is disposed between the semiconductor device and the central guard ring, and the second flanking ring is disposed outside of the central guard ring. The integrated circuit further includes means for reducing resistance across a region that is located between the first and second flanking rings. The introduction of the means for reducing resistance increases the high current performance of the guard ring structure in accordance with the present invention.